By Charles E. Stroud
A contemporary technological increase is the paintings of designing circuits to check themselves, often called a integrated Self-Test (BIST). This thought used to be first proposed round 1980 and has grown to turn into one of many most crucial trying out suggestions on the present time, in addition to for the long run. This publication is written from a designer's point of view and describes the foremost BIST ways which have been proposed and carried out in view that 1980, besides their merits and barriers. The BIST techniques comprise the integrated common sense Block Observer, pseudo-exhaustive BIST innovations, round BIST, scan-based BIST, BIST for normal buildings, BIST for FPGAs and CPLDs, mixed-signal BIST, and the mixing of BIST with concurrent fault detection options for online trying out. specific consciousness is paid to system-level use of BIST as a way to maximize the advantages of BIST via diminished trying out time and value in addition to excessive diagnostic answer. the writer spent 15 years as a clothier at Bell Labs the place he designed over 20 construction VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of varied kinds for normal constructions and normal sequential good judgment, together with the first BIST for Random entry thoughts (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the previous 10 years in academia the place his learn and improvement maintains to target BIST, together with the first BIST for FPGAs and CPLDs besides persevered paintings within the quarter of BIST for basic sequential common sense and mixed-signal structures. He holds 10 US patents (with five extra pending) for numerous varieties of BIST methods. for that reason, the writer brings a distinct mix of information and adventure to this sensible advisor for designers, try engineers, product engineers, approach diagnosticians, and executives.
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Additional info for A Designer s Guide to Built-in Self-Test
Bridging faults that create a feedback loop in a combinational logic circuit, where the output of an inverting combinational logic circuit is shorted to its input, may be more difficult to detect. In the case of a feedback bridging fault on a single inverting gate, such as an inverter, the feedback can cause an intermediate voltage at the output of the gate which results in both PFETs and NFETs partially conducting. This results in a current path from to during steady-state that can be detected by testing techniques.
4d. These are also the same test vectors that detect the transistor stuck-off faults. However, the ordering of the test vectors is critical in the case of the stuck-off fault detection, Also critical is the interleaving of the all 0s test pattern for setting up the necessary logic 1 value at the output of the NOR gate. Therefore, for a K-input static CMOS elementary logic gate (NAND or NOR), a minimum of 2K vectors are required to detect all of the transistor-level faults. For a NAND gate, this set begins with the all 1s test pattern and alternates this test vector with all possible patterns consisting of a single 0 in a field of 1s.
Fault Models and Detection Realistic potential bridging fault sites can be accurately extracted from the physical design by using existing CAD tools developed for capacitance extraction from the physical design database for post-layout timing simulations . By extracting fringe capacitance we determine potential bridging faults on a given mask layer. Extracting overlap capacitance, on the other hand, yields potential bridging faults between mask layers. Using the parallel plate model, overlap capacitance is given by: where A is the area of overlap and d is the distance between the two conductors is the inter-layer dielectric constant).